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1/26 october 2001 AN1177 application note p51xa/psd8xx design guide contents n in-system programming and in-application re- programming C the iap problem C a common solution n physical connections n simple design example C memory map C psdsoft express design entry n enhanced design example C required changes in the psdsoft express design entry C memory map n conclusion n references n appendix a: connecting to a psd813f with no secondary memory flash psd8xx devices are members of a family of flash mem- ory-based peripherals for use with embedded microcontrollers (mcus). these programmable system devices (psds) consist of memory, logic, and i/o. when coupled with a low-cost p51xa mcu, the psd forms a complete embedded flash sys- tem that is 100% in-system programmable (isp) and in-appli- cation programmable (iap). there are many features in the psd silicon and in the psdsoft express development software that make isp easy, regardless of how much experience you have with embedded design. this document offers two designs using a st psd813f2 and a philips p51xa mcu. note that a variety of 8-bit mcu/mpus can be used in place of the philips part. although the specifics of this document are based on the p51xa, this document can be used as a guide for other mcu/mpu applications. the first design is a simple system to get up and running quickly for ba- sic applications or to check out your prototype p51xa hard- ware. the second design illustrates the use of enhanced features of psd in-system programming as applied to the p51xa. you can start with the first design and migrate to the second as your functional requirements grow. there are other members of the psd8xx family, including the psd813f1/f3/ f4/f5, the psd833f2/834f2, and the psd835g2. see the se- lector guide on the website for a comparison of the products. this application note is applicable to all psd8xx family mem- bers. in-system programming and in-application re- programming our industry uses the term in-system programming (isp) in a general sense. isp is applicable to programmable logic, as well as programmable non-volatile memory (nvm). however, an additional term will be used in this document: in-application programming (iap). there are subtle yet significant differences between isp and iap when microcontrollers are involved. isp of memory means that the mcu is off-line and not involved while memory is being programmed. for iap, the mcu partici- pates in programming the memory, which is important for sys- tems that must be online while updating firmware. often, isp is well suited for manufacturing, while iap is appropriate for field
AN1177 - application note 2/26 updates. psd8xx devices are capable of both isp and iap. keep in mind that iap can only program the memory sections of the psd and not the configuration and programmable logic portions. with isp, the entire psd can be erased or programmed. the iap problem typically, a host computer downloads firmware into an embedded flash system through a communication channel that is controlled by the mcu. this channel is usually a uart, but any communication channel that the p51xa supports will do. the p51xa must execute the code that controls the iap process from an independent memory array that is not being erased or programmed. otherwise, boot code and flash memory programming algorithms (iap loader code) will be unavailable to the p51xa. it is absolutely nec- essary to use an alternate memory array (an independent memory that is not being programmed) to store the iap loader code. a system designer must choose the type of alternate memory to store iap loader code (rom, sram, flash, or eeprom); each type has advantages and disadvantages. this alternate memory may reside external to the mcu or on-chip. a top-level view of an embedded iap flash system with external memory is shown in figure 1. figure 1. embedded flash system capable of iap (5 devices) another problem, which is specific to the p51xa architecture, is related to the separate program and data address spaces. the p51xa cannot write to program space, but that is where the flash memory resides that holds p51xa firmware. how can one program flash memory in-system if the p51xa cannot write to program space? a common solution without a psd device, implementing iap with the p51xa can be difficult and time consuming. philips ap- plication note an440 contains a ram loader program (bootstrap loader). it shows how to load code into an external ram over a serial link after power-up and how to switch execution to that ram to complete the boot sequence. this can be a cumbersome and error prone exercise using re-locatable code in volatile memory, which is difficult to debug, vulnerable to power outages, and not supported by all emulators. ad- ditionally, this method restricts the designer to using a uart to implement iap. to overcome the issue of program versus data space, a common practice is to combine the two address spaces, which reduces the total address space of the p51xa by 50%. a better, integrated solution figure 2 shows a two-chip solution using an flash psd813f. this system has ample main flash memory, ai03326b embedded system system i/o cpld p51xa host computer communication channel main flash memory 128 kbytes alternate memory for isp loader code system sram 8 kbytes
3/26 AN1177 - application note a second alternate flash memory to hold the iap loader code and general data, and more sram. all three of these memories can operate independently and concurrently; meaning the mcu can operate from one memory while erasing/writing the other. this allows the mcu to continue normal operation during iap, which is crucial for some applications. this system also has programmable logic, expanded i/o, and de- sign security. the two-chip solution is 100% programmable in the factory or in the field. figure 2. embedded flash system capable of isp (2 devices) note: 1. other members of the psd8xx family offer more flash memory and more sram. 2. only the psd813f1 offers eeprom, while the other members of the psd8xx family offer secondary flash memory. by design, the iap method described above requires mcu participation to exercise a communication channel to implement a download to the main flash memory. the psd8xx also offers an alternative method called in-system programming (isp) to program the psd using a built-in ieee 1149.1 jtag in- terface requiring no mcu participation. this means that a completely blank psd can be soldered into place and the entire chip can be programmed in-system in just a few seconds using sts flashlink? jtag cable and psdsoft express development software. no p51xa firmware needs to be written. just plug in the flashlink cable to your pcs parallel port and begin programming memory, logic, and config- uration. this is a powerful feature of the psd8xx that allows immediate development of application code in your lab, smart manufacturing techniques, and easy field updates. the flashlink? cable and psdsoft express software are available in a kit from the website www.st.com/ psd . figure 3 gives a block diagram of the psd813f for your reference. ai03327b embedded system system i/o jtag p51xa host computer communication channel 128 kbyte flash optional 32 kbyte eeprom/flash optional 2kbyte sram programmable logic i/o psd813f 1,2
AN1177 - application note 4/26 figure 3. top level block diagram of psd8xx physical connections connect your p51xa to the psd8xx as shown in figure 4. the same connections can be used for all of the members of the psd8xx family except the psd835g2, which has more i/o. the jtag programming channel, sram with battery backup, lcd module, and mcu i/o connections are all optional. ai03322b jtag controller cpld 16 output macrocells 24 input macrocells 128 kbyte flash 8 sectors decode pld optional 2 kbyte sram optional 32 kbyte eeprom/flash 4 sectors page reg power mngt device security mcu control mcu address / data pld bus i/o bus i/o port a i/o port b i/o port c i/o port d mcu address / data / control bus psd813f
5/26 AN1177 - application note figure 4. physical connections, p51xa and psd8xxfx simple design example the first design example outlines the steps required to get a p51xa system up and running quickly. a con- nection diagram, memory map, and the necessary design file for the psdsoft express software develop- ment environment are provided. a psd813f2 was used for this example. however, other members of the flash psd family may be used instead, with minor changes to the sample design file. see the selector guide on the website for a comparison of the products. memory map for this simple design, we used a psd813f2 with the following memories: n 128 kbytes main flash memory, broken into eight 16 kbyte segments denoted fs i (i = 1-8) n 32 kbytes boot flash memory, broken into four 8 kbyte segments denoted csboot j (j = 1-4) . the psd813f1 has an eeprom instead of flash memory. therefore, ees j (j = 1-4) would be used in place of csboot j . n 2 kbyte sram (rs0) n 256 byte psd813f configuration register (csiop). note: the psd memory segments are defined in the chip select equations screen in psdsoft express. well use the boot memory to hold the isp boot loader code, p51xa interrupt vectors, and common firm- ware functions. for this example, well execute from secondary flash memory only and leave the main flash memory in data space. lets examine the sample memory map in figure 5. ai03329b psd8xxfx adio0 adio8 adio7 adio6 adio5 adio4 adio3 adio2 adio1 adio15 adio14 adio13 adio12 adio11 adio9 adio10 cntl0 pd0-ale cntl1 reset\ pa0 pa1 pc0/tms pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pa7 pa6 pa5 pa4 pa3 pa2 pc1/tck pc2/vstby pc7 pc6/tdo pc5/tdi pc4/terr pc3/tstat pd2-csi\ pd1-clkin cntl2 30 39 37 36 35 34 33 32 31 45 44 43 42 41 40 49 47 46 9 10 50 48 8 12 11 52 51 20 19 17 14 13 6 5 4 3 2 7 21 22 23 24 25 27 28 29 18 optional jtag port tms tdo tdi terr| tstat tck optional 3.6 v lithium battery or cap wr\ ale p51xa rst\ p51xa assumptions: * the logic levels on the ea\ and busw pins are low at reset. * the bus configuration register (bcr), bits bc2-bc0 are set to 010 to enable an 8-bit data interface and a 20-bit address output. * the bus timing registers (btrh/btrl) are set up such that there are no timing conflicts between the psd8xxfx and the p51xa. connections: philips p51xa mcu and wsi flash psd8xxfx plcc package. note: only the necessary pins on the p51xa are shown. ea\ a8/d4 a7/d3 a6/d2 a5/d1 a4/ d0 a3 a2 a1 a15 a14 a13 a12/d7 a11/d7 a9/d5 a10/d6 psen\ a16 a17 a18 a19 busw rd\ reset\ vcc a0/wrh
AN1177 - application note 6/26 figure 5. memory map, simple p51xa/psd813fx design note the following about the sample memory map shown in figure 5: n it is broken up into sixteen 64 kbyte segments. n all areas, except the unmapped regions and the 80c51xa on-chip ram region, are resident on the psd. n it shows both program space and data space. n the 32 kbytes of the psd813f boot memory is mapped to program space. there are several references to boot memory in this document, but the boot memory is simply a secondary memory that can be used as boot memory or can serve any other purpose. n the main flash memory is mapped to data space so that the contents can be programmed. n the psd control register and sram are in the bottom 64 kbyte segment of data space. note that placing the main flash memory and secondary memory into program space or data space is accomplished with the psd vm register. psdsoft express is used to define the initial value of the vm register when the system powers up or is reset. this initial value is stored in the fusemap that gets pro- grammed into the psd. at runtime, the vm register can be changed by writing to it with the mcu. this is illustrated in the enhanced design of section 4. the boot memory holds the following information: n p51xa reset vector and initialization routines 0:0000 f:ffff 2:ffff f:ffff 2:ffff 0:6000 0:4000 0:1000 0:1900 0:8000 0:2000 0:0000 0:1800 1:0000 2:c000 1:4000 2:4000 2:8000 2:0000 1:8000 1:c000 ai03330b not to scale main flash memory fs7 16 kbytes flash not to scale not to scale boot from here main flash memory fs6 16 kbytes flash main flash memory fs5 16 kbytes flash main flash memory fs4 16 kbytes flash main flash memory fs3 16 kbytes flash main flash memory fs2 16 kbytes flash main flash memory fs1 16 kbytes flash main flash memory fs0 16 kbytes flash unmapped 13 x 64 kbytes unmapped 13 x 64 kbytes unmapped 160 kbytes unmapped 57.75 kbytes unmapped 3 to 3.75 kbytes psd control register (csiop) 256 bytes optional sram (rs0) 2 kbytes 80c51xa on-chip ram 256 bytes to 1 kbyte program space data space optional boot flash/eeprom (csboot0/ees0--8 kbytes) optional boot flash/eeprom (csboot1/ees1--8 kbytes) optional boot flash/eeprom (csboot2/ees2--8 kbytes) optional boot flash/eeprom (csboot3/ees3--8 kbytes)
7/26 AN1177 - application note n p51xa interrupt vectors and service routines n i/o management. since figure 5 is a sample memory map, you may wish to change it. to do so, simply change the chip select equations within the design assistant in psdsoft express. for example, if you have a psd813f part that doesnt contain the optional secondary memory, you will want to have the main flash memory located in program space. see appendix a for a sample memory map for parts with no secondary boot memory. psdsoft express design entry highlights of design entry will be given here. please refer to the psdsoft express user manual for a thor- ough coverage of all the features of psdsoft express. this section is meant to show you just the essentials to get you going. here are the steps: invoke psdsoft express and open a new project. n start psdsoft express. n create a new project. n select your project folder and name the project (in this example, name the project easy51xa in the folder psdsoft\my_project). mcu and psd selection. when you click ok in the new project window, the mcu and psd selec- tion screen appears. when you see this screen, make the following selections: n select an mcu manufacturer and part number. in this example, were using a philips p51xag3x. n for the control signals box, select /wr, /rd, /psen, burst mode n select the psd8xx series for the psd family. n select a psd813f2 and use the 52-pin plcc package (j package). n based on the above selections, the bus width, bus mode, and ale/as active level will be set automatically. n set the main flash memory to data space only and the secondary flash memory to program space only. this is what the screen should look like after youve made the selections:
AN1177 - application note 8/26 now you have your project established based on a psd813f2 and a p51xa. however, there are many other mcu/mpus you could have chosen in place of the p51xa and still have use of this document. click ok and the design parameters window will appear. design parameters. choose use design assistant and click ok to be taken to the pin definitions screen. notice how all the pins functions on the left hand side of the diagram have been assigned for you based on your mcu and psd selection and configuration. to get an idea of how to add a pin function, click on pc3 in the diagram, then dedicated jtag C tstat in the other box and click the add button. your screen should match the one below. continue to add pin functions to match your design. when fin- ished, click next >> to be taken to the design assistant screen. note: there are detailed instructions on how to use this screen and other design assistant screens in the psdsoft express user manual .
9/26 AN1177 - application note page register definition. in this example, the p51xa is assumed to be outputting 20 address bits, pro- viding a one megabyte address space. as such, no page bits are required to extend the address space, so there is nothing to do on this screen at this time except to move on . however, later, you will see how the page register can be used for general logic inputs to the pld. click next >> when finished. chip select equations. use this screen to enter chip-select equations to match your memory map. the entry for the psd sram (rs0) is shown below.
AN1177 - application note 10/26 use the following table to fill in the rest of the chip select equations: table 1. chip select segment hexadecimal start address hexadecimal end address csiop 01800 018ff fs0 10000 13fff fs1 14000 17fff fs2 18000 1bfff fs3 1c000 1ffff fs4 20000 23fff fs5 24000 27fff fs6 28000 2bfff fs7 2c000 2ffff csboot0 00000 01fff csboot1 02000 03fff csboot2 04000 05fff csboot3 06000 07fff
11/26 AN1177 - application note i/o logic and user defined node equations. the i/o logic equations and user defined node equations screens are used to enter equations for the registered logic within the psd. since this docu- ment focuses on issues related to isp and iap, registered logic equations are not covered. however, for more information on entering registered logic equations, refer to the psdsoft express user manual . also, see application note an 1356design guide: psdsoft express , section 5.2 for a tutorial on implementing logic in the cpld. click done and the software will check your design for errors. if you have any errors, go back and fix them. otherwise, you should now see the design flow window: click on additional psd settings in the design flow window and a dialog box will appear. additional psd settings. there are three functions that can be accomplished in this dialog box: 1. setting the security bitblocks all access to the contents of the psds memories by means of jtag or a conventional programmer. that is, once the security bit is set, no programmer can read or copy the configuration or memory contents of the psd. the only way to erase the security bit is to completely erase the psd. 2. specify the ieee 1149.1 jtag user codeallows you to enter a 32-bit code, which can be used for various functions. click on the jtag/isp tab for more details 3. set the internal memories sector protectionsallows the individual memory sectors within the psd to be write protected to prevent accidental data loss. the mcu/mpu cannot change these settings at run- time; only a device programmer can alter these settings. click ok and you will see the design flow again. next, we need to fit the design to silicon. fitting the design to silicon. to fit the design to silicon, click the fit design to silicon box in the de- sign flow. psdsoft express will compile and synthesize the design and create part of the program data
AN1177 - application note 12/26 file (.obj) that will later be programmed into the psd813f2 silicon. when this process is complete, a report will pop up that shows the resulting pin assignments psd usage. this is the fitter report, which you can use to document your design. since you created a project from scratch, you might receive a fitter error. if this is the case, you should check the psdsoft express user manual for further instructions. c code generation. you can take advantage of the provided low-level c code for accessing memory el- ements within the psd by clicking on the generate c code specific to psd box in the design flow win- dow. to get the c functions and headers, specify the folder in which you want the ansi c files to be written. ansi c code functions and headers are generated for you to paste into your p51xa c compiler environment in the folder you specify. simply tailor the code to meet your system needs. see the psdsoft express user manual for details on the c code generation feature. merge mcu firmware with psd. now that the fitting process is complete, psdsoft express has created a fuse pattern that reflects the psd configuration and logic of your design. psdsoft express places this fuse information into a file (the .obj file). however this fuse pattern does not yet contain the p51xa firm- ware. the next step will accomplish this, producing an .obj file that contains the psd configuration and the p51xa firmware. this final .obj file is what gets programmed into the psd. the same .obj file is appended with mcu firmware in the next step below. for this step, merge mcu firmware with psd, you will input the firmware file(s) that contain absolute addresses from your p51xa compiler/linker in intel hex format. the merger will map these file(s) into the memory segments of the psd according to the chip select equations that you entered in the design as- sistant. this mapping process translates the absolute system addresses that p51xa uses into physical internal psd addresses that are used by a programmer to program the psd. the address translation pro- cess is transparent. all you need to do is enter the file(s) that were generated from your p51xa linker into the appropriate boxes and psdsoft express does the rest. go to the design flow window and click the merge mcu firmware with psd box and you should see this: the far left column contains individual psd memory segments. the next column shows the logic equa- tions for selection of each memory segment (shown for reference only). in the middle are the address
13/26 AN1177 - application note ranges that were specified in the chip select equations screen to create the memory map. psdsoft ex- press filled in these address fields for you. psdsoft express expects to find these absolute mcu address- es within your p51xa linker file(s) when they are imported. on the right are boxes where you can type in (or browse for) the name of the file(s) (including path) that indicates the location of your p51xa linker files. notice that you can select motorola s-record or intel hex record for the input type. leave the mapping mode set to direct. now slide the scroll bar down until you see csboot0 and csboot1. type in the name of the file from your p51xa linker that contains the firmware that will boot up your sys- tem. for this example we called it boot.hex. this file can contain very simple p51xa code that configures your system hardware and performs rudimentary tasks to check out your new hardware. in this example, there are 32 kbytes available in secondary flash memory segments csboot0 and csboot1, which is more than enough for this simple boot and test code. after your new hardware is proven, you can add more code to the boot area for advanced tasks, such as implementing a download to main flash memory from a host computer, as shown in the enhanced design of section 4. no file names are required for the main flash memory regions (fs0-fs7) because we are only operating out of boot flash memory for now. click ok , and the address translate process will produce the final .obj file that you can use to program the psd. programming the psd. the .obj file can be programmed into the psd in one of three ways: the st flashlink ? jtag cable, which connects to the pc parallel port. the st psdpro device programmer, which also connects to the pc parallel port. third-party programmers, such as stag and needhams. see the website at www.st.com/psd for a list of compatible third-party programmers. first well show you how to use the flashlink ? jtag cable to program the psd. programming with flashlink ? . connect the flashlink ? cable to your pcs parallel port. click the st jtag/isp box in the design flow window. you will be prompted for the number of devices in the jtag chain on your circuit board. make the appropriate selection and click ok . this document assumes only
AN1177 - application note 14/26 one device is in the jtag chain. if you have more than one device, refer to the psdsoft express user manual . for single device jtag chains, the window will look similar to the following one: to use this window, ensure that the correct programming data file and psd device appear in step 1. for step 2, select the desired operation, the regions of the psd that the operation affects, and the number of jtag pins (4 or 6) to use on the circuit board. before you perform the selected operation, click the properties button. this dialog box allows you to do the following: set port pins: with this screen, you can set up the psds i/o pins during jtag operations. the default (except for the jtag pins) is input, which is usually fine for most pins. (note that the psd will not respond to any non-jtag i/o.) however, sometimes it may be desirable to set a pin or pins to output during jtag. for example, if you have chip-select signal being generated from the psd that selects a device that po- tentially could drive signals on the jtag lines (if you are multiplexing the pins), you would want that chip- select to be inactive during the jtag operation. jtag-isp attributes: this screen allows you to view the device name and instruction register length. this information may be useful to other design programs. user code: basically, by clicking on the user code tab, you are provided with a space to enter an ieee 1149.1 user code that will be compared to the value previously entered in the additional psd settings screen. once you are satisfied with your property settings, click ok to return to the jtag-isp operations win- dow. you can now perform the selected operation by clicking execute . before you leave this screen, you may wish to save your jtag configuration. this can be done in step 3 by clicking on the save button and specifying a file name. this file can be used next time by clicking the retrieve button. programming with psdpro. ensure that the psdpro device programmer is connected to your pcs par- allel port. click on the st conventional programmers box in the design flow window. you will see this:
15/26 AN1177 - application note if this is the first use of the psdpro, click on the htest icon to perform a test of the psdpro and the pc port. after testing, place a psd813f2 into the socket of the psdpro and click on the program icon. (the .obj file is automatically loaded when this process is invoked). the messaging of psdsoft express will in- form you when programming is complete. this window is also helpful even if you do not have a psdpro programmer. you can use this window to see where the merge mcu firmware utility of psdsoft express has placed the p51xa firmware within physical memory of the psd. for example, you can click on the secondary flash memory icon in the tool bar. notice the p51xa reset vector that would be at absolute mcu addresses 0000h and 0002h, translates to psd secondary flash memory physical addresses 20000h and 20002h, respectively. to see how all of your p51xa absolute addresses translated into physical psd memory addresses, click report->address translation . the start and stop addresses in the report are the absolute mcu system addresses that you have specified. the addresses shown in square brackets are direct physical addresses used by a device programmer to access the memory elements of the psd in a linear fashion (a special device programming mode that the mcu cannot access). enhanced design example this second design example builds upon the first to add enhanced features to this isp/iap capable sys- tem. the physical connections between the p51xa and psd813f2 do not change, but the memory map and chip select equations do. the focus of this enhanced design is to show how the memories of the psd813f2 can be used concurrently. this means swapping the boot code out of program space after the initial boot sequence has completed. the boot code can then be updated if desired. required changes in the psdsoft express design entry the steps to implement the second design in psdsoft express are almost identical to those in the first design. in fact, you can repeat the steps outlined in sections 3.2.1 to 3.2.3, except you should give your new project a different name. change the page register definition. for section 3.2.4, you will need to define a logic bit that will allow the swapping of memory segments within the psd during iap. to do so, with the page register defini- tion tab clicked in the design assistant screen, make the following addition: for pgr7, click the logic checkbox and type swap in the name of logic signal column. this bit will be used in the chip select
AN1177 - application note 16/26 equations to implement memory swapping (as shown in the next subsection). this bit can be modified at runtime by writing to its location in the page register within the csiop address space. see the psd8xx family data sheet for details. when you have made the addition, your screen should look like this: modify the chip select equations. the chip selects equations need to be modified (from what they were in section 3.2.5) to match the situational memory maps outlined in figure 6 to figure 9 in section 4.2. that is, the memory map that is presented to the mcu will vary dynamically based on the settings of the vm register and pgr7 (swap) of the page register. in order to make the memory maps of section 4.2 work, csboot0, csboot1, and fs7 need to be modified. below, the modified csboot0 is shown as an ex- ample.
17/26 AN1177 - application note continue to modify csboot1 and fs7 according to the following screen captures: the steps outlined in sections 3.2.6 to 3.2.9 can be repeated for the enhanced design example at this time. for section 3.2.10, when mapping the p51xa firmware in the address translate utility of psdsoft
AN1177 - application note 18/26 express for this second design example, you still do not need to specify any hex file for the psd main flash memory area. you only need to specify the p51xa linker file(s) for the secondary flash memory area (as in the first simple design) because the p51xa will execute code from secondary flash memory and download to main flash memory. see the next subsection for more details. memory map the boot sequence and memory swap is a four-step process, as shown in figure 6 to figure 9. for more information on both the page register and vm register, see the data sheets and the psdsoft express user manual . memory map configuration at boot-up. figure 6 (next page) shows how the memory map looks at system power-on or at system reset. the swap bit is one of the eight internal psd page register bits, whose value is zero by default. the swap bit is an example of how the page register bits can be imple- mented for uses other than memory paging. the vm register controls which space (program or data) the psd memories appear in and can be set prior to runtime using psdsoft express configuration. the vm register resides in the psd and can be accessed at any time by the p51xa. (see the psd8xx data sheets.) heres what the p51xa does upon power-up or reset: n boot from flash memory boot csboot0 at address 0h n perform a checksum of main flash memory n download main flash memory from a host computer if needed and validate contents.
19/26 AN1177 - application note figure 6. memory map, enhanced design at boot-up/isp memory map configuration after moving the main flash. the next step is to move the main flash memory from data space to program space. to do so, while executing out of the boot flash memory, write 06h to the vm register. you will now have the memory map shown in figure 7. 0:0000 f:ffff 2:ffff f:ffff 2:ffff 0:6000 0:4000 0:1000 0:1900 0:8000 0:2000 0:0000 0:1800 1:0000 2:c000 1:4000 2:4000 2:8000 2:0000 1:8000 1:c000 ai03334 not to scale main flash memory fs7 16 kbytes flash not to scale not to scale boot from here main flash memory fs6 16 kbytes flash main flash memory fs5 16 kbytes flash main flash memory fs4 16 kbytes flash main flash memory fs3 16 kbytes flash main flash memory fs2 16 kbytes flash main flash memory fs1 16 kbytes flash main flash memory fs0 16 kbytes flash unmapped 13 x 64 kbytes unmapped 13 x 64 kbytes unmapped 160 kbytes unmapped 57.75 kbytes unmapped 3 to 3.75 kbytes psd control register (csiop) 256 bytes optional sram (rs0) 2 kbytes 80c51xa on-chip ram 256 bytes to 1 kbyte program space data space swap = 0 vm register = 12h optional boot flash/eeprom (csboot0/ees0--8 kbytes) optional boot flash/eeprom (csboot1/ees1--8 kbytes) optional boot flash/eeprom (csboot2/ees2--8 kbytes) optional boot flash/eeprom (csboot3/ees3--8 kbytes)
AN1177 - application note 20/26 figure 7. memory map after moving the main flash memory to program space memory map configuration after setting the swap bit. next, we want to swap main and secondary flash memory and transfer execution to main flash memory s egment fs7. to do so, the swap bit must be set to hi to re-map the flash memory boot segments csboot0/csboot1 out of the mcu boot area and replace it with main flash memory segment fs7, as shown in figure 8. so that no program continuity is lost, the instruction that sets the swap bit is executed from csboot0 and the next contiguous instruction must be in fs7. for example, if the instruction that executes the swap is at location 1000h in csboot0, then fs7 must contain the next instruction to be executed at location 1002h. 0:0000 f:ffff 2:ffff f:ffff 2:ffff 0:6000 0:4000 0:1000 0:1900 0:8000 0:2000 0:0000 0:1800 1:0000 2:c000 1:4000 2:4000 2:8000 2:0000 1:8000 1:c000 ai03335b not to scale main flash memory fs7 16 kbytes flash not to scale not to scale execute from here main flash memory fs6 16 kbytes flash main flash memory fs5 16 kbytes flash main flash memory fs4 16 kbytes flash main flash memory fs3 16 kbytes flash main flash memory fs2 16 kbytes flash main flash memory fs1 16 kbytes flash main flash memory fs0 16 kbytes flash unmapped 13 x 64 kbytes unmapped 13 x 64 kbytes unmapped 185.75 kbytes unmapped 32 kbytes unmapped 3 to 3.75 kbytes psd control register (csiop) 256 bytes optional sram (rs0) 2 kbytes 80c51xa on-chip ram 256 bytes to 1 kbyte program space data space swap = 0 vm register = 06h optional boot flash/eeprom (csboot0/ees0--8 kbytes) optional boot flash/eeprom (csboot1/ees1--8 kbytes) optional boot flash/eeprom (csboot2/ees2--8 kbytes) optional boot flash/eeprom (csboot3/ees3--8 kbytes)
21/26 AN1177 - application note figure 8. memory map after setting the swap bit memory map configuration after moving the boot flash memory to data space. the final step is to move the secondary flash memory to data space so that it can be updated if desired. to move the secondary flash memory to data space, write 0ch to the vm register. once the vm register has been written, you can program either half of the secondary flash memory, depending on how the unlock bit is set. figure 9 shows the final state of the memory map. 0:0000 f:ffff 2:ffff f:ffff 2:ffff 0:6000 0:4000 0:1000 0:1900 0:8000 2:e000 0:0000 0:1800 1:0000 2:c000 1:4000 2:4000 2:8000 2:0000 1:8000 1:c000 ai03336b not to scale main flash memory fs7 16 kbytes flash not to scale not to scale execute from here main flash memory fs6 16 kbytes flash main flash memory fs5 16 kbytes flash main flash memory fs4 16 kbytes flash main flash memory fs3 16 kbytes flash main flash memory fs2 16 kbytes flash main flash memory fs1 16 kbytes flash main flash memory fs0 16 kbytes flash unmapped 13 x 64 kbytes unmapped 13 x 64 kbytes unmapped 185.75 kbytes unmapped 32 kbytes unmapped 3 to 3.75 kbytes psd control register (csiop) 256 bytes optional sram (rs0) 2 kbytes 80c51xa on-chip ram 256 bytes to 1 kbyte program space data space swap = 0 vm register = 06h optional boot flash/eeprom (csboot0/ees0---8 kbytes) optional boot flash/eeprom (csboot1/ees1--8 kbytes) optional boot flash/eeprom (csboot2/ees2--8 kbytes) optional boot flash/eeprom (csboot3/ees3--8 kbytes)
AN1177 - application note 22/26 figure 9. memory map after moving the boot flash memory to data space in this final configuration, the p51xa has available: n 16 kbytes main flash memory in the boot area (00000h-03fffh) n 112 kbytes main flash memory in program space (10000h-2bfffh) n 2 kbytes of sram in addition to the sram that resides on the p51xa n 16 kbytes of boot flash memory for general data storage (04000h-07fffh) n 16 kbytes of boot flash memory for boot and iap loader code (2c000h-2ffffh). each time this p51xa system gets reset or goes through a power-on cycle, the psd presents the memory map of figure 6 to the mcu, and the boot sequence is repeated. conclusion these examples are just two of an endless number of ways to configure the flash psd for your system. concurrent memories with a built-in programmable decoder at the segment level offer excellent flexibility. also, as you have seen with the swap and unlock bits, the page register bits do not have to be used just for paging through memory. the ability to expand your system does not require any physical connec- tion changes, as everything is configured internal to the psd. and finally, the jtag channel can be used 0:0000 f:ffff 2:ffff f:ffff 2:ffff 0:6000 0:4000 0:1000 0:1900 0:8000 2:e000 0:0000 0:1800 1:0000 2:c000 1:4000 2:4000 2:8000 2:0000 1:8000 1:c000 ai03337b not to scale main flash memory fs7 16 kbytes flash not to scale not to scale execute from here main flash memory fs6 16 kbytes flash main flash memory fs5 16 kbytes flash main flash memory fs4 16 kbytes flash main flash memory fs3 16 kbytes flash main flash memory fs2 16 kbytes flash main flash memory fs1 16 kbytes flash main flash memory fs0 16 kbytes flash unmapped 13 x 64 kbytes unmapped 13 x 64 kbytes unmapped 144 kbytes unmapped 48 kbytes unmapped 3 to 3.75 kbytes psd control register (csiop) 256 bytes optional sram (rs0) 2 kbytes 80c51xa on-chip ram 256 bytes to 1 kbyte program space data space swap = 0 vm register = 0ch unmapped 8.75 kbytes 2:c000 0:4000 unmapped 16 kbytes optional boot flash/eeprom (csboot0/e es0--8 kbytes) optional boot flash/eeprom (csboot1/e es1--8 kbytes) optional boot flash/eeprom (csboot2/e es2--8 kbytes) optional boot flash/eeprom (csboot3/e es3--8 kbytes)
23/26 AN1177 - application note for isp anytime, and anywhere, with no participation from the mcu. all of these features are crosschecked under the psdsoft express development environment to minimize your effort to design a flash memory p51xa system capable of iap. references psd8xx family data sheets for detailed psd8xx information psdsoft express user manual for details on how to use the design software application note an1153: jtag isp information: flash psd for detailed use of the jtag port application note an1171: flash psd cpld primer appendix a: connecting to a psd813f with no secondary memory the following is a sample memory map for connecting to a psd813f with no secondary memory (such as the psd813f3 or psd813f5). this memory map assumes you have downloaded the main flash memory with the flashlink cable or you have booted from a separate prom and have downloaded the flash memory using the mcu. in either case, you must change your design to account for the different segment locations.
AN1177 - application note 24/26 figure 10. memory map for a psd813f device (with no secondary boot memory) 0:0000 f:ffff 2:ffff f:ffff 2:ffff 0:1000 0:1900 0:0000 0:1800 1:c000 0:4000 1:4000 1:8000 1:0000 0:8000 0:c000 ai03338b not to scale main flash memory fs7 16 kbytes flash not to scale not to scale main flash memory fs6 16 kbytes flash main flash memory fs5 16 kbytes flash main flash memory fs4 16 kbytes flash main flash memory fs3 16 kbytes flash main flash memory fs2 16 kbytes flash main flash memory fs1 16 kbytes flash main flash memory fs0 16 kbytes flash unmapped 13 x 64 kbytes unmapped 13 x 64 kbytes unmapped 169.75 kbytes unmapped 64 kbytes unmapped 3 to 3.75 kbytes psd control register (csiop) 256 bytes optional sram (rs0) 2 kbytes 80c51xa on-chip ram 256 bytes to 1 kbyte program space data space 2:0000
25/26 AN1177 - application note table 2. document revision history date rev. description of revision nov-2000 2.0 document written in the wsi format 30-oct-2001 3.0 document converted to the st format
AN1177 - application note 26/26 for current information on psd products, please consult our pages on the world wide web: www.st.com/psd if you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses: apps.psd@st.com (for application support) ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies austalia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com

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